In recent years, as advances are being made in the scaling-down and multi-layered formation of wirings in a semiconductor integrated circuit device, a so-called damacene technique has been studied, as described, for example, by T. Saito et. al., in Proceedings of International Interconnect Technology Conference, 1998, pp. 160-162 and the like, in which after formation of a groove for wirings in an insulating film, a conductive film is buried inside the groove.
In Japanese laid-open patent Application No. Hei 8 (1996)-222568, a technique is described wherein a groove for wiring is formed in an insulating film and a barrier layer made of a TiN (titanium nitride) thin film is formed according to a CVD (chemical vapor deposition) method, after which a copper thin film is formed on the barrier layer and the copper thin film is etched back, followed by further formation of a protective film made of a TiN thin film and subsequent etching to leave the protective film on the resultant copper thin film wiring.
In the technical report of Mitsubishi Electric Corporation in 1997, pp 333-336, a technique is described wherein a barrier layer, such as TiWN or the like, is provided on the upper surface of a copper damascene wiring.